POEMS Semiconductor Spring School 2026

Andreas Gerstlauer - UT Austin | Traditional semiconductor scaling reaching physical and technological limits has driven the need for increasing specialization and heterogeneity in computer system and systems-on-chip (SoC). The use of custom compute units, such as GPUs or dedicated hardware accelerators is commonplace in many domains such as machine learning (ML). At the same time, increasing heterogeneity creates challenges for designing and managing such complex systems and chips, where use of ML techniques has seen a lot of excitement and promise. In this talk, we will discuss recent trends in heterogeneous system architectures and their design, including distributed, chiplet-based architectures, near-memory computing, as well as emerging approximate and neuromorphic or brain-inspired computing paradigms to achieve high energy efficiency. We will discuss both system design for ML applications as well as use of ML for advanced system design and runtime management. In the process, we will review both traditional approaches for system-level and hardware/software co-design of computer systems, as well as state-of-the-art approaches including open challenges and opportunities.

André Cardoso - INL |  Electronic Packaging encompasses all technologies and processes that provide the physical support to the chip, establish its connections to the outside and ensures its mechanical and chemical protection. In a broader sense, Packaging bridges the gap between the micro and nanoscale of today’s chips and the functionalization scale – the human scale. As chips become more complex and demanding, its connection to the outside world faces new challenges. Thus, in recent decades, the importance of Packaging in the electronic industry has grown exponentially and today, from design to implementation, Packaging demands a truly interdisciplinary approach. This session aims provide an historical overview of Packaging, its evolutions in response to the challenges of chips, and to highlight the vital role that multidisciplinary engineering plays. 

Eoin O’Toole - Amkor Technology Portugal | Advanced packaging is the bridge between Semiconductor foundry technologies measured in Nanometers and the application PCB technologies measured in fractions of mm. As foundry technology advances further into single digits nanometers, advanced packaging technology has been required to develop to an extent which blurs the boundaries between the two. The focus of this seminar will be the manufacturing processes which enable the development of advanced packaging, it will become clear that a wide range of disciplines are required to build the bridge. 

Nuno Lourenço – CircuitLeap | Analog and mixed-signal integrated circuit design remains one of the most challenging domains in electronic design automation, characterized by highly non-linear behaviors, expensive simulations, and a strong dependence on expert knowledge. Over the past decade, artificial intelligence techniques have progressively reshaped this landscape, evolving from optimization-driven approaches to learning-based design methodologies. This talk presents a structured overview of the application of artificial intelligence to analog and RF IC design, drawing from a body of work spanning evolutionary optimization, surrogate modeling, machine learning–based synthesis, and physics-aware modeling techniques. 

Manuel Oliveira - Axelera AI | The deployment of AI at the edge presents unique design challenges that differ fundamentally from datacenter-scale acceleration. Stringent constraints on power consumption, area, and latency shape architectural decisions from the earliest stages and propagate throughout the entire silicon development flow. This talk examines how these constraints influence the complete journey from architecture definition to physical implementation of edge AI accelerators. Drawing from practical experience in edge AI chip development, we explore key architectural trade-offs, including compute versus memory bandwidth optimisation, dataflow strategies, precision choices, and power-performance balance. The presentation bridges high-level architectural decisions with their implications on RTL design, verification methodologies, and physical implementation. Through concrete examples, we illustrate how AI-specific requirements—from handling sparse neural networks to managing diverse workload characteristics—demand adaptations in traditional chip design methodologies. The session provides insights into the multidisciplinary nature of AI accelerator design, where algorithm understanding, hardware architecture, and silicon implementation expertise must converge to enable efficient inference at the edge. 

Pedro Rito - University of Aveiro | The IEEE HART initiative aims to address the limited student access to the design, fabrication, and testing of integrated circuits at universities. There is a clear need for structured training in Integrated Circuit Design and affordable access to fabrication shuttles (MPW). The main objective of the initiative is to provide motivated students with facilitated access to chip fabrication, accompanied by specialized mentorship, enabling them to gain hands-on experience across the full cycle of design, implementation, and testing of integrated circuits.

Stefan Wallentowitz - Munich University of Applied Sciences | For decades, custom silicon design was the privilege of a few, guarded by prohibitive licensing costs and non-disclosure agreements. This lecture explores the paradigm shift enabled by the convergence of three critical pillars: open-source processor design IP with RISC-V, open-source EDA toolchains, and open-source manufacturing. In this session, we will demystify the complete “RTL to GDSII" flow. Attendees will be guided through the lifecycle of a digital chip, starting with the architectural flexibility of open-source RISC-V cores. We will demonstrate how modern open-source tools handle synthesis, floorplanning, placement, routing, and signoff—all without proprietary software. The session concludes with a case study of a successful tapeout, proving that you can design and manufacture an open-source system-on-chip easily.