POEMS Semiconductor Spring School 2026

The electronics industry faces significant challenges, including complex supply chain dependencies on essential materials, energy-intensive processes, the growing global e-waste crisis, which exceeds 50 million tonnes annually, and the technical complexities of adopting circular design principles without compromising performance or cost-effectiveness. Attempting to integrate sustainability into this already complex scenario also introduces issues related to standards compliance and the substantial capital investments necessary for a sustainable manufacturing transition. On the other hand, developing new concepts to bring intelligence to everyday objects is very appealing in markets such as smart packaging and wearables, which include biosensors. Given that implementing intelligence in such sectors requires addressing the challenge of creating low-cost or disposable devices, it is crucial to develop new concepts when designing electronic devices for these sectors. Cost-effectiveness and functional efficiency are essential factors to consider. In this context, printed and hybrid electronics offer unique advantages for sustainability, including additive manufacturing processes that minimise material waste, compatibility with flexible and biodegradable substrates, low-temperature processing requirements, and the potential for distributed manufacturing that reduces transportation impacts. This represents a $15 billion market segment projected to reach $89 billion by 2030. (Luís Pereira - AlmaScience)

Traditional semiconductor scaling reaching physical and technological limits has driven the need for increasing specialization and heterogeneity in computer system and systems-on-chip (SoC). The use of custom compute units, such as GPUs or dedicated hardware accelerators is commonplace in many domains such as machine learning (ML). At the same time, increasing heterogeneity creates challenges for designing and managing such complex systems and chips, where use of ML techniques has seen a lot of excitement and promise. In this talk, we will discuss recent trends in heterogeneous system architectures and their design, including distributed, chiplet-based architectures, near-memory computing, as well as emerging approximate and neuromorphic or brain-inspired computing paradigms to achieve high energy efficiency. We will discuss both system design for ML applications as well as use of ML for advanced system design and runtime management. In the process, we will review both traditional approaches for system-level and hardware/software co-design of computer systems, as well as state-of-the-art approaches including open challenges and opportunities. (Andreas Gerstlauer - UT Austin)

Electronic Packaging encompasses all technologies and processes that provide the physical support to the chip, establish its connections to the outside and ensures its mechanical and chemical protection. In a broader sense, Packaging bridges the gap between the micro and nanoscale of today’s chips and the functionalization scale – the human scale. As chips become more complex and demanding, its connection to the outside world faces new challenges. Thus, in recent decades, the importance of Packaging in the electronic industry has grown exponentially and today, from design to implementation, Packaging demands a truly interdisciplinary approach. This session aims provide an historical overview of Packaging, its evolutions in response to the challenges of chips, and to highlight the vital role that multidisciplinary engineering plays. (André Cardoso - INL)

Advanced packaging is the bridge between Semiconductor foundry technologies measured in Nanometers and the application PCB technologies measured in fractions of mm. As foundry technology advances further into single digits nanometers, advanced packaging technology has been required to develop to an extent which blurs the boundaries between the two. The focus of this seminar will be the manufacturing processes which enable the development of advanced packaging, it will become clear that a wide range of disciplines are required to build the bridge. (Eoin O’Toole - Amkor Technology Portugal)

Analog and mixed-signal integrated circuit design remains one of the most challenging domains in electronic design automation, characterized by highly non-linear behaviors, expensive simulations, and a strong dependence on expert knowledge. Over the past decade, artificial intelligence techniques have progressively reshaped this landscape, evolving from optimization-driven approaches to learning-based design methodologies. This talk presents a structured overview of the application of artificial intelligence to analog and RF IC design, drawing from a body of work spanning evolutionary optimization, surrogate modeling, machine learning–based synthesis, and physics-aware modeling techniques. (Nuno Lourenço – CircuitLeap)

The deployment of AI at the edge presents unique design challenges that differ fundamentally from datacenter-scale acceleration. Stringent constraints on power consumption, area, and latency shape architectural decisions from the earliest stages and propagate throughout the entire silicon development flow. This talk examines how these constraints influence the complete journey from architecture definition to physical implementation of edge AI accelerators. Drawing from practical experience in edge AI chip development, we explore key architectural trade-offs, including compute versus memory bandwidth optimisation, dataflow strategies, precision choices, and power-performance balance. The presentation bridges high-level architectural decisions with their implications on RTL design, verification methodologies, and physical implementation. Through concrete examples, we illustrate how AI-specific requirements—from handling sparse neural networks to managing diverse workload characteristics—demand adaptations in traditional chip design methodologies. The session provides insights into the multidisciplinary nature of AI accelerator design, where algorithm understanding, hardware architecture, and silicon implementation expertise must converge to enable efficient inference at the edge. (Manuel Oliveira - Axelera AI)

This session explores the complete journey of photonic integrated circuits from early concept to mass production, highlighting both the technological strengths and the practical limitations that shape commercialization. Key design challenges such as filtering, polarization control, and variability are discussed alongside the capabilities and trade-offs of major integration platforms, including silicon photonics, silicon nitride, thin-film lithium niobate, and emerging ferroelectric technologies. The session further examines manufacturing access, fabrication lead times, and cost barriers, and how these factors influence development cycles and business planning. Attention is also given to the critical roles of electronics co-integration, testing, qualification, packaging, and assembly in enabling scalable, high-volume production. Overall, the session provides a realistic, end-to-end view of what it takes to bring photonic integrated circuits successfully to market. (António Teixeira - PICadvanced)

The rapid expansion of the Internet of Things (IoT), with billions of battery-powered devices deployed in environments where battery replacement is impractical or impossible, has created a critical need for radical reductions in power consumption at the silicon level. While conventional power management ICs operate transistors in strong inversion, achieving nanoampere-level quiescent currents demands a fundamentally different design philosophy: full-subthreshold operation, where all transistors work in the weak inversion region. This approach introduces significant design challenges, including increased sensitivity to process variations, reduced speed, and the need for novel circuit topologies that remain robust across wide temperature and voltage ranges. In this talk, we will walk through the complete journey of developing an ultra-low-power chip for IoT — from identifying the market opportunity and defining product specifications, through the circuit-level innovations required to achieve reliable subthreshold operation, to silicon validation and the path toward commercialization. Using the development of Nanopower Semiconductor's nPZero power supervisor IC as a case study, we will discuss the key technical decisions at each stage of the design cycle, including architecture trade-offs, layout considerations specific to ultra-low-power analog design, and the iterative process of test chip tapeouts leading to a full mask production run. We will also address the broader context of building an IC design team and product development capability within Portugal's growing semiconductor ecosystem, offering a practitioner's perspective on how academic foundations in microelectronics translate into real-world chip development. (Américo Dias - Nanopower Semiconductor)

The IEEE HART initiative aims to address the limited student access to the design, fabrication, and testing of integrated circuits at universities. There is a clear need for structured training in Integrated Circuit Design and affordable access to fabrication shuttles (MPW). The main objective of the initiative is to provide motivated students with facilitated access to chip fabrication, accompanied by specialized mentorship, enabling them to gain hands-on experience across the full cycle of design, implementation, and testing of integrated circuits. (Pedro Rito - University of Aveiro)

For decades, custom silicon design was the privilege of a few, guarded by prohibitive licensing costs and non-disclosure agreements. This lecture explores the paradigm shift enabled by the convergence of three critical pillars: open-source processor design IP with RISC-V, open-source EDA toolchains, and open-source manufacturing. In this session, we will demystify the complete “RTL to GDSII" flow. Attendees will be guided through the lifecycle of a digital chip, starting with the architectural flexibility of open-source RISC-V cores. We will demonstrate how modern open-source tools handle synthesis, floorplanning, placement, routing, and signoff—all without proprietary software. The session concludes with a case study of a successful tapeout, proving that you can design and manufacture an open-source system-on-chip easily. (Stefan Wallentowitz - Munich University of Applied Sciences)

We will present recent advances in quantum technologies, focusing on their impact on secure communications. In particular, we discuss how progress in quantum computing may jeopardize the security of current cryptographic systems, and how quantum communication techniques, such as quantum key distribution, can be used to assure secure key exchange. We also address how these quantum cryptographic keys can support secure communication and computation services. (Armando Pinto - Universidade de Aveiro)

Photonic assembly and packaging are complex, multi-disciplinary processes that play a vital role in ensuring the correct functioning, reliability, and commercial viability of photonic integrated circuits. This talk will present and discuss PIC design considerations and practical experiences that enable the successful delivery of a functional demonstrator or prototype device, while maintaining compatibility with future large-scale manufacturing. (Karol Obara - PHIX Photonics Assembly)